| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| open-sdr/openwifi | CShellPython | 3.3k | +16 | 551 | +1 |
| darklife/darkriscv | VerilogSystemVerilogTeX | 1.7k | +10 | 257 | +2 |
| SI-RISCV/e200_opensource | VerilogCAssembly | 2.4k | +8 | 975 | 0 |
| The-OpenROAD-Project/OpenROAD | VerilogC++Tcl | 986 | +8 | 372 | +3 |
| WangXuan95/FPGA-USB-Device | Verilog | 261 | +8 | 57 | +1 |
| chipsalliance/chisel | ScalaC++Python | 3.2k | +8 | 541 | +2 |
| The-OpenROAD-Project/OpenLane | PythonTclDockerfile | 1k | +7 | 330 | +1 |
| analogdevicesinc/hdl | VerilogTclMakefile | 1.2k | +5 | 1.4k | +3 |
| SpinalHDL/VexRiscv | AssemblyScalaC++ | 2k | +4 | 354 | 0 |
| olofk/serv | VerilogPythonTcl | 1.1k | +4 | 155 | +1 |
| stnolting/neorv32 | VHDLCMakefile | 1.2k | +4 | 172 | 0 |
| ultraembedded/biriscv | VerilogC++Other | 665 | +2 | 125 | +1 |
| WangXuan95/FPGA-SATA-HBA | SystemVerilogVerilogVHDL | 57 | +2 | 15 | 0 |
| WangXuan95/FPGA-MPEG2-encoder | VerilogBatchfile | 61 | +2 | 10 | 0 |
| splinedrive/kianRiscV | AGS ScriptAssemblyC | 312 | +2 | 22 | 0 |
| WangXuan95/FPGA-Gzip-compressor | VerilogPythonOther | 57 | +2 | 11 | 0 |
| ulixxe/usb_cdc | Verilog | 124 | +2 | 5 | 0 |
| projf/projf-explore | SystemVerilogTclC++ | 455 | +1 | 47 | 0 |
| ultraembedded/cores | VerilogCC++ | 575 | +1 | 185 | +2 |
| syntacore/scr1 | SystemVerilogCMakefile | 689 | +1 | 240 | 0 |
| WilsonChen003/HDLGen | VerilogPerl | 58 | +1 | 17 | 0 |
| furrtek/VGChips | VerilogPython | 131 | +1 | 12 | 0 |
| risclite/R8051 | VerilogC | 125 | +1 | 39 | 0 |
| chipsalliance/chisel3 | ScalaC++Python | 3.2k | 0 | 541 | 0 |
| SpinalHDL/SpinalHDL | ScalaVerilogPython | 1.4k | 0 | 276 | 0 |