This is stars and forks stats for /WilsonChen003/HDLGen repository. As of 03 May, 2024 this repository has 58 stars and 17 forks.
HDLGen from Wilson Chen 2022~2023 Overview HDLGen is a tool for HDL(mainly for Verilog) generation, it enables embedded Perl or Python scripts in Verilog source code, and support Perl style variable anyway, to generate desired HDL in an easy and efficient way. It supports all syntax and data structure of Perl or Python, and has a few predefined functions for signal define, module instance, port connection etc. This tool also supports extended API functions in Perl style, for any function...
HDLGen from Wilson Chen 2022~2023 Overview HDLGen is a tool for HDL(mainly for Verilog) generation, it enables embedded Perl or Python scripts in Verilog source code, and support Perl style variable anyway, to generate desired HDL in an easy and efficient way. It supports all syntax and data structure of Perl or Python, and has a few predefined functions for signal define, module instance, port connection etc. This tool also supports extended API functions in Perl style, for any function...
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