The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

PythonTclDockerfileMakefileVerilogJavaScriptOthermagicasicrtlverilogvlsifoundryyosysklayoutcaravelnetgensystem-on-chipopenroadopenramskywater130nmsoc-designrtl2gds
This is stars and forks stats for /The-OpenROAD-Project/OpenLane repository. As of 26 Apr, 2024 this repository has 1010 stars and 330 forks.

OpenLane OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, KLayout and a number of custom scripts for design exploration and optimization. The flow performs all ASIC implementation steps from RTL all the way down to GDSII. You can check out the documentation, including in-depth guides and reference manuals at ReadTheDocs. Quick-start Guide If you just want to try OpenLane...
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