chipsalliance/chisel

Chisel: A Modern Hardware Design Language

ScalaC++PythonMakefileDockerfileVerilogscalachip-generatorchiselrtlchisel3firrtlverilog
This is stars and forks stats for /chipsalliance/chisel repository. As of 24 Apr, 2024 this repository has 3212 stars and 541 forks.

The Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators...
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