darklife/darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

VerilogSystemVerilogTeXTclShellcpufpgacoreprocessorriscvrtlverilogrisc-vrv32isoftcoreprocessor-designrv32e
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DarkRISCV Opensource RISC-V implemented from scratch in one night! Table of Contents DarkRISCV Table of Contents Introduction History Project Background Directory Description "src" Directory "sim" Directory "rtl" Directory "board" Directory Implementation Notes* Development Tools Development Boards FuseSoC support Creating a RISCV from scratch Academic Papers and Applications Performance Comparisons Acknowledgments References Introduction Developed in a magic night of 19 Aug, 2018 between 2am and...
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