ultraembedded/cores

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Various HDL (Verilog) IP Cores Github: http://github.com/ultraembedded/cores Cloning This repo contains submodules, to clone them; git clone --recursive https://github.com/ultraembedded/cores.git Catalogue Name Description asram16_axi4 AXI4 -> Async SRAM (16-bit) Interface dbg_bridge UART -> AXI4 Debug Bridge dvi_framebuffer DVI/HDMI framebuffer with AXI-4 bus master ftdi_async_bridge FTDI Asynchronous FIFO Interface (Wishbone) ftdi_bridge FTDI Asynchronous/Synchronous FIFO Interface (AXI-4) ft60x_axi FTDI...