This is stars and forks stats for /ultraembedded/biriscv repository. As of 29 Apr, 2024 this repository has 665 stars and 125 forks.
biRISC-V - 32-bit dual issue RISC-V CPU Github: http://github.com/ultraembedded/biriscv Features 32-bit RISC-V ISA CPU core. Superscalar (dual-issue) in-order 6 or 7 stage pipeline. Support RISC-V’s integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr). Branch prediction (bimodel/gshare) with configurable depth branch target buffer (BTB) and return address stack (RAS). 64-bit instruction fetch, 32-bit data access. 2 x integer ALU (arithmetic, shifters and...
biRISC-V - 32-bit dual issue RISC-V CPU Github: http://github.com/ultraembedded/biriscv Features 32-bit RISC-V ISA CPU core. Superscalar (dual-issue) in-order 6 or 7 stage pipeline. Support RISC-V’s integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr). Branch prediction (bimodel/gshare) with configurable depth branch target buffer (BTB) and return address stack (RAS). 64-bit instruction fetch, 32-bit data access. 2 x integer ALU (arithmetic, shifters and...
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