| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| riscv-mcu/e203_hbirdv2 | VerilogCAssembly | 923 | 0 | 287 | 0 |
| pConst/basic_verilog | VerilogVHDLSystemVerilog | 1.3k | 0 | 303 | 0 |
| ultraembedded/riscv | VerilogC++C | 933 | 0 | 192 | 0 |
| VUnit/vunit | VHDLPythonOther | 645 | 0 | 236 | 0 |
| open-sdr/openwifi-hw | VerilogTclOther | 534 | 0 | 199 | 0 |
| ZipCPU/zipcpu | VerilogC++C | 1.1k | 0 | 149 | 0 |
| chipsalliance/f4pga-examples | VerilogTclOther | 247 | 0 | 72 | 0 |
| WangXuan95/BSV_Tutorial_cn | BluespecShellAssembly | 392 | 0 | 35 | 0 |
| jhshi/openofdm | VerilogVHDLOther | 306 | 0 | 169 | 0 |
| WangXuan95/FPGA-SDcard-Reader | VerilogBatchfile | 153 | 0 | 42 | 0 |
| hughperkins/VeriGPU | SystemVerilogC++Python | 418 | 0 | 50 | 0 |
| The-OpenROAD-Project/OpenROAD-flow-scripts | VerilogSourcePawnCoq | 208 | 0 | 226 | 0 |
| OpenTimer/OpenTimer | VerilogC++Tcl | 472 | 0 | 139 | 0 |
| logisim-evolution/logisim-evolution | JavaHTMLCSS | 3.7k | 0 | 506 | 0 |
| f-of-e/f-of-e-tools | VerilogMakefileC | 7 | 0 | 36 | 0 |
| lvyufeng/step_into_mips | Verilog | 598 | 0 | 142 | 0 |
| sudhamshu091/32-Verilog-Mini-Projects | VerilogPython | 342 | 0 | 84 | 0 |
| clash-lang/clash-compiler | HaskellCTcl | 1.3k | 0 | 143 | 0 |
| circuitvalley/USB_C_Industrial_Camera_FPGA_USB3 | VerilogCOther | 605 | 0 | 107 | 0 |
| racerxdl/riskow | VerilogCMakefile | 120 | 0 | 8 | 0 |
| chipsalliance/f4pga-xc-fasm2bels | VerilogPythonTcl | 8 | 0 | 12 | 0 |
| omarelhedaby/CNN-FPGA | VerilogPythonHTML | 223 | 0 | 62 | 0 |
| zachjs/sv2v | HaskellSystemVerilogVerilog | 404 | 0 | 46 | 0 |
| xiaop1/Verilog-Practice | VerilogV | 559 | 0 | 163 | 0 |
| PrincetonUniversity/openpiton | AssemblyVerilogC | 523 | 0 | 191 | 0 |