| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| open-sdr/openwifi | CShellPython | 3.3k | +16 | 551 | +1 |
| ultraembedded/biriscv | VerilogC++Other | 665 | +2 | 125 | +1 |
| Xilinx/Vitis_Accel_Examples | MakefileC++SystemVerilog | 436 | +1 | 190 | 0 |
| pConst/basic_verilog | VerilogVHDLSystemVerilog | 1.3k | 0 | 303 | 0 |
| SymbiFlow/yosys-f4pga-plugins | VerilogC++Tcl | 76 | 0 | 47 | 0 |
| open-sdr/openwifi-hw | VerilogTclOther | 534 | 0 | 199 | 0 |
| chipsalliance/yosys-f4pga-plugins | VerilogC++Tcl | 76 | 0 | 47 | 0 |
| ZipCPU/wb2axip | VerilogMakefileC++ | 384 | 0 | 90 | 0 |
| f4pga/prjuray | SystemVerilogPythonTcl | 52 | 0 | 11 | 0 |
| 19801201/SpinalHDL_CNN_Accelerator | ScalaPython | 93 | 0 | 26 | 0 |
| hdl-util/hdmi | SystemVerilogPythonStata | 911 | 0 | 98 | 0 |
| fredrequin/verilator_xilinx | Verilog | 22 | 0 | 1 | 0 |
| ultraembedded/openlogicbit | VerilogSystemVerilogOther | 81 | 0 | 8 | 0 |
| WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial | BatchfileCOther | 169 | 0 | 33 | 0 |
| fpgasystems/Coyote | SystemVerilogC++Tcl | 137 | 0 | 40 | 0 |
| jofrfu/tinyTPU | VHDLCPython | 305 | 0 | 58 | 0 |
| eugene-tarassov/vivado-risc-v | TclCJava | 606 | 0 | 147 | 0 |
| jge162/ScoreBoard-wTimer | VerilogVShell | 22 | 0 | 7 | 0 |
| leonow32/verilog-fpga | VerilogPythonBatchfile | 17 | 0 | 1 | 0 |