SymbiFlow/yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

VerilogC++TclMakefilePythontoolchainfpgaedaxilinxyosysxilinx-fpgayosys-pluginf4pga
This is stars and forks stats for /SymbiFlow/yosys-f4pga-plugins repository. As of 25 Apr, 2024 this repository has 76 stars and 47 forks.

Yosys F4PGA Plugins This repository contains plugins for Yosys developed as part of the F4PGA project. Design introspection plugin Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a selection of objects. Additionally provides functions to convert selection on TCL lists. Following commands are added with the plugin: get_cells get_nets get_pins get_ports get_count selection_to_tcl_list FASM plugin Writes out the design's fasm features based...
Read on GithubGithub Stats Page
repotechsstarsweeklyforksweekly
IObundle/iob-cacheVerilogMakefileTeX1220290
newaetech/chipwhispererVHDLCPython945+4266+2
chxuan/vimplusVim ScriptShellPython3.8k+21.1k-1
ryanoasis/vim-deviconsVim ScriptPython5.4k+2258+1
amix/vimrcVim ScriptVim SnippetRuby29.4k+237.2k+4
macvim-dev/macvimVim ScriptCObjective-C7.3k+8684-1
usnistgov/macos_securityYAMLPythonCSS1.3k+91630
microsoft/onnxruntimeC++CPython10.6k+1432.3k+16
catchorg/Catch2C++CMakePython17.1k+203k0
Tencent/ncnnC++CGLSL18k04k0