ZipCPU/wb2axip

Bus bridges and other odds and ends

VerilogMakefileC++VHDLOtherfpgagplv3xilinxwishbonexilinx-vivadowishbone-busaxi-bus
This is stars and forks stats for /ZipCPU/wb2axip repository. As of 02 May, 2024 this repository has 384 stars and 90 forks.

WB2AXIP: Bus interconnects, bridges, and other components The bus components and bridges within this repository are unique in that they are all designed for 100% throughput with no throughput overhead. They are also unique in that the vast majority of the cores within have all been formally verified. Where the protocol allows it, such as with AXI4, AXI-lite, and Wishbone B4 pipelined, multiple transactions may be in flight at a time so that protocol handling doesn't stall the bus. This is uncommon...
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