| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| unicorn-engine/unicorn | CPythonJava | 6.7k | +15 | 1.2k | -1 |
| darklife/darkriscv | VerilogSystemVerilogTeX | 1.7k | +10 | 257 | +2 |
| chipsalliance/rocket-chip | ScalaPythonC++ | 2.8k | +7 | 1k | +5 |
| SpinalHDL/VexRiscv | AssemblyScalaC++ | 2k | +4 | 354 | 0 |
| stnolting/neorv32 | VHDLCMakefile | 1.2k | +4 | 172 | 0 |
| mikeroyal/RISC-V-Guide | Assembly | 366 | +3 | 27 | 0 |
| riscv/meta-riscv | BitBakeC++Makefile | 309 | +2 | 124 | +2 |
| ultraembedded/biriscv | VerilogC++Other | 665 | +2 | 125 | +1 |
| splinedrive/kianRiscV | AGS ScriptAssemblyC | 312 | +2 | 22 | 0 |
| syntacore/scr1 | SystemVerilogCMakefile | 689 | +1 | 240 | 0 |
| sergeykhbr/riscv_vhdl | VerilogC++SystemVerilog | 537 | +1 | 96 | 0 |
| chipsalliance/Cores-SweRV | SystemVerilogCPerl | 730 | 0 | 194 | 0 |
| riscv-mcu/e203_hbirdv2 | VerilogCAssembly | 923 | 0 | 287 | 0 |
| ultraembedded/riscv | VerilogC++C | 933 | 0 | 192 | 0 |
| Tencent/ncnn | C++CGLSL | 18k | 0 | 4k | 0 |
| riscv-boom/riscv-boom | ScalaCShell | 1.5k | 0 | 381 | 0 |
| pulp-platform/riscv-dbg | SystemVerilogCMakefile | 150 | 0 | 61 | 0 |
| openhwgroup/core-v-mcu | SystemVerilogCC++ | 146 | 0 | 51 | 0 |
| openhwgroup/cv32e40p | SystemVerilogCPython | 780 | 0 | 338 | 0 |
| chipsalliance/Cores-SweRV-EL2 | SystemVerilogPythonPerl | 194 | 0 | 55 | 0 |
| f-of-e/f-of-e-tools | VerilogMakefileC | 7 | 0 | 36 | 0 |
| sifive/ProcKami | CoqMakefile | 23 | 0 | 4 | 0 |
| sifive/RiscvSpecFormal | HaskellShellC++ | 72 | 0 | 7 | 0 |
| capstone-engine/capstone | CC++C# | 6.6k | 0 | 1.5k | 0 |
| pulp-platform/pulp_soc | SystemVerilog | 62 | 0 | 74 | 0 |