chipsalliance/Cores-SweRV

VeeR EH1 core

SystemVerilogCPerlMakefileAssemblyVerilogOtherfpgaprocessorriscvrtlriscrisc-vopen-source-hardwarefusesocverilatorriscv32western-digitalaxi4ahb-liteasic-designveer
This is stars and forks stats for /chipsalliance/Cores-SweRV repository. As of 27 Apr, 2024 this repository has 730 stars and 194 forks.

VeeR EH1 RISC-V Core This repository contains the VeeR EH1 design RTL. License By contributing to this project, you agree that your contribution is governed by Apache-2.0. Files under the tools directory may be available under a different license. Please review individual files for details. Directory Structure ├── configs # Configurations Dir │   └── snapshots # Where generated configuration files are created ├── design # Design root dir │   ├── dbg ...
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