sergeykhbr/riscv_vhdl

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System-On-Chip template based on synthesizable processor compliant with the RISC-V architecture. Howto build FPGA bitstream or RTL simulation: To build KC705 bitstream file: $ cd sv/prj/impl/kc705 $ make To build and run full system unisim RTL simulation: $ cd sv/prj/impl/asic_sim $ make build $ make gui To build and run precise SystemC simulation (see github actions): $ cmake -S ./debugger/cmake -B build $ cd build $ make $ cd linuxbuild/bin $ ./run_sysc_river_x1_gui.sh Note:...