sifive/RiscvSpecFormal

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

HaskellShellC++MakefileNixhardwarecoqriscvhardware-designsformal-verificationriscv-simulator
This is stars and forks stats for /sifive/RiscvSpecFormal repository. As of 30 Apr, 2024 this repository has 72 stars and 7 forks.

Formal Specification of RISC-V ISA in Kami Table of Contents 1. Organization 1.1. FuncUnits directory 1.2. Top-level directory and files This project gives the formal specification of RISC-V ISA in Kami. In particular, it gives the semantics for RV32GC and RV64GC ISAs with User-mode, Supervisor-mode and Machine-mode instructions and the Zam extension (unaligned atomics). Installation instructions are available in INSTALL.adoc. 1. Organization The semantics are organized into two parts, the ProcKami/FuncUnits directory,...
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