ultraembedded/riscv

This is stars and forks stats for /ultraembedded/riscv repository. As of 20 Apr, 2024 this repository has 933 stars and 192 forks.

RISC-V Core Github: http://github.com/ultraembedded/riscv A 32-bit RISC-V core written in Verilog and an instruction set simulator supporting RV32IM. This core has been tested against a co-simulation model and exercised on FPGA. For a higher performance dual issue CPU with branch prediction, see my latest RISC-V core here; http://github.com/ultraembedded/biriscv Overview Features 32-bit RISC-V ISA CPU core. Support RISC-V integer (I), multiplication and division (M), and CSR instructions (Z) extensions...