openhwgroup/cv32e40p

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OpenHW Group CORE-V CV32E40P RISC-V IP CV32E40P is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements the RV32IM[F|Zfinx]C instruction set architecture, and the PULP custom extensions for achieving higher code density, performance, and energy efficiency [1], [2]. It started its life as a fork of the OR10N CPU core that is based on the OpenRISC ISA. Then, under the name of RI5CY, it became a RISC-V core (2016), and it has been maintained by the PULP platform...