| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| The-OpenROAD-Project/OpenLane | PythonTclDockerfile | 1k | +7 | 330 | +1 |
| openhwgroup/cva6 | SystemVerilogCAssembly | 1.8k | +7 | 549 | +1 |
| olofk/serv | VerilogPythonTcl | 1.1k | +4 | 155 | +1 |
| ultraembedded/biriscv | VerilogC++Other | 665 | +2 | 125 | +1 |
| ulixxe/usb_cdc | Verilog | 124 | +2 | 5 | 0 |
| ultraembedded/cores | VerilogCC++ | 575 | +1 | 185 | +2 |
| WilsonChen003/HDLGen | VerilogPerl | 58 | +1 | 17 | 0 |
| furrtek/VGChips | VerilogPython | 131 | +1 | 12 | 0 |
| pulp-platform/axi | SystemVerilogStataShell | 791 | 0 | 222 | +3 |
| chipsalliance/Cores-SweRV | SystemVerilogCPerl | 730 | 0 | 194 | 0 |
| ultraembedded/riscv | VerilogC++C | 933 | 0 | 192 | 0 |
| slaclab/surf | VHDLPythonSystemVerilog | 248 | 0 | 47 | 0 |
| VUnit/vunit | VHDLPythonOther | 645 | 0 | 236 | 0 |
| pulp-platform/axi_mem_if | SystemVerilog | 27 | 0 | 21 | 0 |
| pulp-platform/axi_node | SystemVerilog | 17 | 0 | 35 | 0 |
| hughperkins/VeriGPU | SystemVerilogC++Python | 418 | 0 | 50 | 0 |
| chipsalliance/Cores-SweRV-EL2 | SystemVerilogPythonPerl | 194 | 0 | 55 | 0 |
| ucb-bar/gemmini | ScalaShell | 536 | 0 | 117 | 0 |
| clash-lang/clash-compiler | HaskellCTcl | 1.3k | 0 | 143 | 0 |
| google/gf180mcu-pdk | Makefile | 292 | 0 | 57 | 0 |
| google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | Verilog | 16 | 0 | 9 | 0 |
| google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | Verilog | 22 | 0 | 10 | 0 |
| google/skywater-pdk-sky130-raw-data | Jupyter Notebook | 39 | 0 | 18 | 0 |
| stnolting/neorv32-verilog | VerilogVHDLShell | 28 | 0 | 8 | 0 |
| chipsalliance/Cores-VeeR-EH1 | SystemVerilogCPerl | 730 | 0 | 194 | 0 |