stnolting/neorv32-verilog

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NEORV32 in Verilog Prerequisites Configuration Conversion Simulation Evaluation This repository shows how to convert a complex VHDL design into a synthesizable plain Verilog netlist module using GHDL's synthesis feature. The example in this repository is based on the NEORV32 RISC-V Processor, which is written in platform-independent VHDL. The resulting Verilog module can be instantiated within an all-Verilog design and can be successfully simulated and synthesized - tested with Xilinx Vivado and...