| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| chipsalliance/rocket-chip | ScalaPythonC++ | 2.6k | +15 | 961 | +2 |
| alexforencich/verilog-axi | VerilogPythonMakefile | 878 | +11 | 327 | +1 |
| chipsalliance/chisel | ScalaC++Python | 3k | +10 | 513 | +1 |
| YosysHQ/picorv32 | VerilogAssemblyC | 2.3k | +8 | 630 | +2 |
| The-OpenROAD-Project/OpenROAD | VerilogC++Tcl | 789 | +7 | 303 | +2 |
| The-OpenROAD-Project/OpenLane | VerilogPythonTcl | 871 | +3 | 301 | 0 |
| google/CFU-Playground | VerilogC++Python | 360 | +3 | 90 | -1 |
| EttusResearch/uhd | VerilogC++C | 774 | +2 | 591 | +1 |
| analogdevicesinc/hdl | VerilogTclMakefile | 1.1k | +1 | 1.3k | +2 |
| IObundle/iob-mem | VerilogPythonMakefile | 28 | +1 | 19 | 0 |
| PKUanonym/REKCARC-TSC-UHT | HTMLCC++ | 28.1k | 0 | 7.2k | 0 |
| Xilinx/Vitis_Accel_Examples | MakefileC++SystemVerilog | 386 | 0 | 175 | 0 |
| chipsalliance/chisel3 | ScalaC++Python | 3k | 0 | 513 | 0 |
| apache/tvm-vta | ScalaC++Tcl | 183 | 0 | 65 | 0 |
| pulp-platform/axi_riscv_atomics | SystemVerilogStataVerilog | 36 | 0 | 9 | 0 |
| efabless/caravel_user_project | VerilogTcl | 112 | 0 | 267 | 0 |
| MiSTer-devel/PSX_MiSTer | VHDLVerilogSystemVerilog | 151 | 0 | 41 | 0 |
| aws/aws-fpga | VHDLSystemVerilogV | 1.3k | 0 | 506 | 0 |
| OSCPU/ysyx-workbench | ShellMakefileC++ | 43 | 0 | 40 | 0 |
| SpinalHDL/SpinalHDL | ScalaVerilogPython | 1.2k | 0 | 256 | 0 |
| chipsalliance/Cores-SweRV | SystemVerilogCPerl | 663 | 0 | 181 | 0 |
| riscv-mcu/e203_hbirdv2 | VerilogCAssembly | 743 | 0 | 235 | 0 |
| danfoisy/vdatp | VerilogHTMLC++ | 256 | 0 | 24 | 0 |
| SI-RISCV/e200_opensource | VerilogCAssembly | 2.2k | 0 | 946 | 0 |
| pConst/basic_verilog | VerilogVHDLHTML | 1.1k | 0 | 273 | 0 |