| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| openhwgroup/cva6 | SystemVerilogCTcl | 1.7k | +5 | 506 | +4 |
| lowRISC/opentitan | SystemVerilogCPython | 1.8k | +4 | 539 | +3 |
| lowRISC/ibex | SystemVerilogPythonC++ | 946 | +3 | 407 | +3 |
| EttusResearch/uhd | VerilogC++C | 773 | +3 | 591 | +1 |
| analogdevicesinc/hdl | VerilogTclMakefile | 1.1k | +2 | 1.3k | +4 |
| chipsalliance/caliptra-rtl | SystemVerilogAssemblyC | 15 | +2 | 4 | 0 |
| Xilinx/Vitis_Accel_Examples | MakefileC++SystemVerilog | 386 | 0 | 175 | 0 |
| muneeb-mbytes/pulpino__spi_master__ip_verification | SystemVerilogOther | 10 | 0 | 5 | 0 |
| pulp-platform/fpga-support | SystemVerilogMakefileTcl | 5 | 0 | 9 | 0 |
| pulp-platform/axi_riscv_atomics | SystemVerilogStataVerilog | 36 | 0 | 9 | 0 |
| pulp-platform/axi | SystemVerilogStataShell | 645 | 0 | 184 | 0 |
| MiSTer-devel/PSX_MiSTer | VHDLVerilogSystemVerilog | 151 | 0 | 41 | 0 |
| aws/aws-fpga | VHDLSystemVerilogV | 1.3k | 0 | 506 | 0 |
| SpinalHDL/SpinalHDL | ScalaVerilogPython | 1.2k | 0 | 256 | 0 |
| chipsalliance/Cores-SweRV | SystemVerilogCPerl | 663 | 0 | 181 | 0 |
| pulp-platform/snitch | SystemVerilogCRust | 169 | 0 | 32 | 0 |
| projf/projf-explore | SystemVerilogC++Tcl | 405 | 0 | 48 | 0 |
| danfoisy/vdatp | VerilogHTMLC++ | 256 | 0 | 24 | 0 |
| pConst/basic_verilog | VerilogVHDLHTML | 1.1k | 0 | 273 | 0 |
| T-head-Semi/openc910 | VerilogAssemblyC | 772 | 0 | 207 | 0 |
| pulp-platform/common_verification | SystemVerilogShell | 28 | 0 | 10 | 0 |
| MoonbaseOtago/vroom | VerilogSystemVerilogHTML | 371 | 0 | 12 | 0 |
| slaclab/surf | VHDLPythonSystemVerilog | 208 | 0 | 43 | 0 |
| IObundle/iob-cache | VerilogMakefileTeX | 103 | 0 | 26 | 0 |
| newaetech/chipwhisperer | VHDLCAssembly | 850 | 0 | 253 | 0 |