| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| renode/renode | RobotFrameworkC#Python | 1.2k | +13 | 223 | 0 |
| enjoy-digital/litex | CPythonSystemVerilog | 2.4k | +9 | 474 | +1 |
| lowRISC/ibex | SystemVerilogPythonC++ | 1.1k | +8 | 445 | +2 |
| YosysHQ/yosys | C++VerilogPython | 2.8k | +8 | 790 | -2 |
| srg320/Saturn_MiSTer | SystemVerilogVerilogVHDL | 133 | +7 | 18 | +2 |
| RobertPeip/Mister64 | VHDLVerilogSystemVerilog | 97 | +7 | 9 | +2 |
| verilator/verilator | C++SystemVerilogPerl | 1.7k | +6 | 460 | 0 |
| T-head-Semi/openc910 | VerilogAssemblyC | 899 | +5 | 248 | +3 |
| darklife/darkriscv | VerilogSystemVerilogTeX | 1.7k | +5 | 255 | +1 |
| AngeloJacobo/DDR3_Controller | VerilogTeXSystemVerilog | 21 | +5 | 5 | +2 |
| pConst/basic_verilog | VerilogVHDLSystemVerilog | 1.3k | +4 | 302 | +2 |
| openhwgroup/cva6 | SystemVerilogCAssembly | 1.8k | +4 | 547 | +3 |
| aws/aws-fpga | VHDLSystemVerilogV | 1.4k | +3 | 515 | +1 |
| chipsalliance/Cores-SweRV | SystemVerilogCPerl | 727 | +3 | 191 | 0 |
| slaclab/surf | VHDLPythonSystemVerilog | 247 | +3 | 47 | 0 |
| pulp-platform/fpnew | SystemVerilogPython | 310 | +3 | 87 | 0 |
| openhwgroup/cvfpu | SystemVerilogPython | 310 | +3 | 87 | 0 |
| vortexgpgpu/vortex | VerilogPostScriptC++ | 829 | +3 | 179 | +1 |
| pulp-platform/pulp | SystemVerilogVerilogTcl | 363 | +3 | 102 | 0 |
| openhwgroup/cvw | AssemblyCSystemVerilog | 125 | +3 | 74 | 0 |
| EttusResearch/uhd | VerilogC++C | 838 | +2 | 616 | +2 |
| lowRISC/opentitan | SystemVerilogCPython | 2k | +2 | 597 | 0 |
| pulp-platform/common_cells | SystemVerilogTclC++ | 352 | +2 | 114 | +1 |
| cxlisme/FPGA-proj | VHDLVerilogV | 144 | +2 | 38 | 0 |
| nand2mario/nestang | VerilogSystemVerilogC++ | 175 | +2 | 17 | +1 |