| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| darklife/darkriscv | VerilogSystemVerilogTeX | 1.7k | +10 | 257 | +2 |
| The-OpenROAD-Project/OpenROAD | VerilogC++Tcl | 986 | +8 | 372 | +3 |
| WangXuan95/FPGA-USB-Device | Verilog | 261 | +8 | 57 | +1 |
| chipsalliance/chisel | ScalaC++Python | 3.2k | +8 | 541 | +2 |
| The-OpenROAD-Project/OpenLane | PythonTclDockerfile | 1k | +7 | 330 | +1 |
| chipsalliance/rocket-chip | ScalaPythonC++ | 2.8k | +7 | 1k | +5 |
| youngsoft/MyLinearLayout | Objective-COther | 4.3k | +2 | 903 | +1 |
| ultraembedded/cores | VerilogCC++ | 575 | +1 | 185 | +2 |
| syntacore/scr1 | SystemVerilogCMakefile | 689 | +1 | 240 | 0 |
| WilsonChen003/HDLGen | VerilogPerl | 58 | +1 | 17 | 0 |
| chipsalliance/chisel3 | ScalaC++Python | 3.2k | 0 | 541 | 0 |
| pulp-platform/axi | SystemVerilogStataShell | 791 | 0 | 222 | +3 |
| SpinalHDL/SpinalHDL | ScalaVerilogPython | 1.4k | 0 | 276 | 0 |
| chipsalliance/Cores-SweRV | SystemVerilogCPerl | 730 | 0 | 194 | 0 |
| merbanan/rtl_433 | CCMakeOther | 5.2k | 0 | 1.2k | 0 |
| riscv-boom/riscv-boom | ScalaCShell | 1.5k | 0 | 381 | 0 |
| open-sdr/openwifi-hw | VerilogTclOther | 534 | 0 | 199 | 0 |
| bitbrain/jekyll-dash | SCSSJavaScriptHTML | 259 | 0 | 104 | 0 |
| WangXuan95/FPGA-SDcard-Reader | VerilogBatchfile | 153 | 0 | 42 | 0 |
| The-OpenROAD-Project/OpenROAD-flow-scripts | VerilogSourcePawnCoq | 208 | 0 | 226 | 0 |
| chipsalliance/Cores-SweRV-EL2 | SystemVerilogPythonPerl | 194 | 0 | 55 | 0 |
| avashist003/SystemVerilog_Design_Verification | SystemVerilog | 19 | 0 | 3 | 0 |
| ainfosec/FISSURE | PythonC++C | 1.4k | 0 | 72 | 0 |
| WangXuan95/USTC-RVSoC | SystemVerilogAssemblyTcl | 267 | 0 | 65 | 0 |
| ucb-bar/constellation | ScalaC++Python | 121 | 0 | 18 | 0 |