| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| ultraembedded/biriscv | VerilogC++Other | 665 | +2 | 125 | +1 |
| ultraembedded/cores | VerilogCC++ | 575 | +1 | 185 | +2 |
| chipsalliance/Cores-SweRV | SystemVerilogCPerl | 730 | 0 | 194 | 0 |
| ultraembedded/riscv | VerilogC++C | 933 | 0 | 192 | 0 |
| ZipCPU/zipcpu | VerilogC++C | 1.1k | 0 | 149 | 0 |
| chipsalliance/Cores-SweRV-EL2 | SystemVerilogPythonPerl | 194 | 0 | 55 | 0 |
| fredrequin/verilator_xilinx | Verilog | 22 | 0 | 1 | 0 |
| verilator/verilator | C++SystemVerilogPerl | 1.8k | 0 | 462 | 0 |
| tvlad1234/FakePGA | CMakeC++C | 149 | 0 | 5 | 0 |
| chipsalliance/Cores-VeeR-EH1 | SystemVerilogCPerl | 730 | 0 | 194 | 0 |
| chipsalliance/Cores-VeeR-EL2 | SystemVerilogPythonPerl | 194 | 0 | 55 | 0 |