chipsalliance/Cores-VeeR-EL2

VeeR EL2 Core

SystemVerilogPythonPerlCMakefileVerilogOtherfpgaprocessorriscvrtlrisc-vopen-source-hardwarefusesocverilatorriscv32western-digitalaxi4ahb-liteasic-designel2
This is stars and forks stats for /chipsalliance/Cores-VeeR-EL2 repository. As of 29 Apr, 2024 this repository has 194 stars and 55 forks.

VeeR EL2 RISC-V Core This repository contains the VeeR EL2 RISC-V Core design RTL. License By contributing to this project, you agree that your contribution is governed by Apache-2.0. Files under the tools directory may be available under a different license. Please review individual files for details. Directory Structure ├── configs # Configurations Dir │   └── snapshots # Where generated configuration files are created ├── design # Design root dir │  ...
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