| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| RT-Thread/rt-thread | CAssemblyHTML | 8.8k | +16 | 4.7k | +3 |
| mortbopet/Ripes | C++AssemblyCMake | 2.1k | +12 | 249 | 0 |
| darklife/darkriscv | VerilogSystemVerilogTeX | 1.7k | +10 | 257 | +2 |
| SI-RISCV/e200_opensource | VerilogCAssembly | 2.4k | +8 | 975 | 0 |
| renode/renode | RobotFrameworkC#Python | 1.3k | +8 | 227 | +2 |
| openhwgroup/cva6 | SystemVerilogCAssembly | 1.8k | +7 | 549 | +1 |
| olofk/serv | VerilogPythonTcl | 1.1k | +4 | 155 | +1 |
| stnolting/neorv32 | VHDLCMakefile | 1.2k | +4 | 172 | 0 |
| mikeroyal/RISC-V-Guide | Assembly | 366 | +3 | 27 | 0 |
| riscv/meta-riscv | BitBakeC++Makefile | 309 | +2 | 124 | +2 |
| ultraembedded/biriscv | VerilogC++Other | 665 | +2 | 125 | +1 |
| openhwgroup/core-v-verif | AssemblySystemVerilogC | 328 | +1 | 183 | -1 |
| syntacore/scr1 | SystemVerilogCMakefile | 689 | +1 | 240 | 0 |
| lowRISC/ibex | SystemVerilogPythonC++ | 1.1k | 0 | 447 | +2 |
| OpenXiangShan/XiangShan | ScalaPythonOther | 4k | 0 | 545 | 0 |
| chipsalliance/Cores-SweRV | SystemVerilogCPerl | 730 | 0 | 194 | 0 |
| riscv-mcu/e203_hbirdv2 | VerilogCAssembly | 923 | 0 | 287 | 0 |
| ultraembedded/riscv | VerilogC++C | 933 | 0 | 192 | 0 |
| firesim/firesim | ScalaPythonC++ | 752 | 0 | 196 | 0 |
| firesim/icenet | ScalaC++Verilog | 12 | 0 | 20 | 0 |
| hughperkins/VeriGPU | SystemVerilogC++Python | 418 | 0 | 50 | 0 |
| chipsalliance/Cores-SweRV-EL2 | SystemVerilogPythonPerl | 194 | 0 | 55 | 0 |
| alibaba/AliOS-Things | CHTMLC++ | 4.5k | 0 | 1.1k | 0 |
| f-of-e/f-of-e-tools | VerilogMakefileC | 7 | 0 | 36 | 0 |
| rcore-os/rCore-Tutorial-v3 | RustMakefileOther | 1.2k | 0 | 346 | 0 |