| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| DeFiMasterd/PancakeX-ASTRA-V2-BSC-Sniping-Bot | TclPython | 380 | +78 | 267 | +19 |
| Yapote/ARBITRUM-Grid-Trading-Bot-GMX | TclPython | 83 | +54 | 50 | +22 |
| Meetytoes/ARBITRUM-Token-Trading-Bot-ZEUS | TclPython | 77 | +53 | 50 | +28 |
| rdbende/Sun-Valley-ttk-theme | TclPythonJavaScript | 1.1k | +18 | 68 | 0 |
| alexforencich/verilog-axi | VerilogPythonMakefile | 878 | +11 | 327 | +1 |
| The-OpenROAD-Project/OpenROAD | VerilogC++Tcl | 789 | +7 | 303 | +2 |
| macports/macports-ports | TclCShell | 1.3k | +4 | 1.2k | +5 |
| The-OpenROAD-Project/OpenLane | VerilogPythonTcl | 871 | +3 | 301 | 0 |
| openhwgroup/cva6 | SystemVerilogCTcl | 1.7k | +3 | 506 | +1 |
| analogdevicesinc/hdl | VerilogTclMakefile | 1.1k | +1 | 1.3k | +2 |
| slaclab/ruckus | TclPythonMakefile | 52 | +1 | 25 | 0 |
| Digilent/digilent-xdc | Tcl | 357 | +1 | 557 | +2 |
| SpinalHDL/VexRiscv | AssemblyScalaC++ | 1.8k | 0 | 327 | 0 |
| apache/tvm-vta | ScalaC++Tcl | 183 | 0 | 65 | 0 |
| lowRISC/ibex | SystemVerilogPythonC++ | 946 | 0 | 407 | 0 |
| pulp-platform/fpga-support | SystemVerilogMakefileTcl | 5 | 0 | 9 | 0 |
| efabless/caravel_user_project | VerilogTcl | 112 | 0 | 267 | 0 |
| aws/aws-fpga | VHDLSystemVerilogV | 1.3k | 0 | 506 | 0 |
| OSVVM/OSVVM | VHDLTcl | 189 | 0 | 50 | 0 |
| jlord/git-it-electron | PerlHTMLVim Script | 4.3k | 0 | 1.2k | 0 |
| pulp-platform/snitch | SystemVerilogCRust | 169 | 0 | 33 | 0 |
| projf/projf-explore | SystemVerilogC++Tcl | 405 | 0 | 48 | 0 |
| riscv-mcu/e203_hbirdv2 | VerilogCAssembly | 743 | 0 | 235 | 0 |
| git/git | CShellPerl | 45.7k | 0 | 24.9k | 0 |
| sqlcipher/sqlcipher | CTclShell | 5.4k | 0 | 1.2k | 0 |