| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| FreeRTOS/FreeRTOS | CHTMLAssembly | 4k | +20 | 1.3k | +2 |
| darklife/darkriscv | VerilogSystemVerilogTeX | 1.7k | +10 | 257 | +2 |
| alexforencich/verilog-ethernet | VerilogPythonTcl | 1.7k | +9 | 541 | +4 |
| pawelsalawa/sqlitestudio | CC++Yacc | 3.8k | +9 | 513 | +3 |
| The-OpenROAD-Project/OpenROAD | VerilogC++Tcl | 986 | +8 | 372 | +3 |
| rdbende/Sun-Valley-ttk-theme | TclPythonJavaScript | 1.4k | +8 | 86 | 0 |
| RobertPeip/Mister64 | VHDLVerilogSystemVerilog | 112 | +8 | 10 | +1 |
| The-OpenROAD-Project/OpenLane | PythonTclDockerfile | 1k | +7 | 330 | +1 |
| openhwgroup/cva6 | SystemVerilogCAssembly | 1.8k | +7 | 549 | +1 |
| lammps/lammps | C++TclPython | 1.8k | +6 | 1.6k | +4 |
| analogdevicesinc/hdl | VerilogTclMakefile | 1.2k | +5 | 1.4k | +3 |
| alexforencich/verilog-axi | VerilogPythonMakefile | 1.1k | +5 | 361 | 0 |
| VerticalResearchGroup/miaow | VerilogStataC | 836 | +5 | 225 | 0 |
| SpinalHDL/VexRiscv | AssemblyScalaC++ | 2k | +4 | 354 | 0 |
| jlord/git-it-electron | PerlHTMLVim Script | 4.5k | +4 | 1.2k | 0 |
| pulp-platform/common_cells | SystemVerilogTclC++ | 356 | +4 | 117 | +2 |
| olofk/serv | VerilogPythonTcl | 1.1k | +4 | 155 | +1 |
| ThrowTheSwitch/CMock | CRubyPascal | 595 | +4 | 300 | +5 |
| lnis-uofu/OpenFPGA | VerilogC++Tcl | 643 | +4 | 134 | 0 |
| mirkat1206/2021_Spring_NCTU_ICLAB | VerilogSystemVerilogPython | 110 | +4 | 26 | 0 |
| HolographicWings/TOTK-Mods-collection | TclShell | 2.4k | +4 | 230 | +3 |
| pulp-platform/pulpissimo | SystemVerilogCTcl | 318 | +3 | 146 | +1 |
| PacktPublishing/Learn-FPGA-Programming | VHDLVerilogV | 133 | +3 | 60 | +1 |
| macports/macports-ports | TclCShell | 1.3k | +2 | 1.2k | +3 |
| efabless/caravel | VerilogTclPython | 195 | +2 | 55 | 0 |