| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| ghdl/ghdl | VHDLAdaC | 2k | +13 | 332 | +1 |
| SpinalHDL/VexRiscv | AssemblyScalaC++ | 2k | +4 | 354 | 0 |
| stnolting/neorv32 | VHDLCMakefile | 1.2k | +4 | 172 | 0 |
| nickg/nvc | VHDLCM4 | 532 | +2 | 75 | 0 |
| sergeykhbr/riscv_vhdl | VerilogC++SystemVerilog | 537 | +1 | 96 | 0 |
| SpinalHDL/SpinalHDL | ScalaVerilogPython | 1.4k | 0 | 276 | 0 |
| slaclab/surf | VHDLPythonSystemVerilog | 248 | 0 | 47 | 0 |
| tomas-fryza/digital-electronics-1 | VHDLTclOther | 55 | 0 | 229 | 0 |
| VUnit/vunit | VHDLPythonOther | 645 | 0 | 236 | 0 |
| open-sdr/openwifi-hw | VerilogTclOther | 534 | 0 | 199 | 0 |
| logisim-evolution/logisim-evolution | JavaHTMLCSS | 3.7k | 0 | 506 | 0 |
| antonblanchard/microwatt | VerilogVHDLC | 569 | 0 | 96 | 0 |
| clash-lang/clash-compiler | HaskellCTcl | 1.3k | 0 | 143 | 0 |
| airhdl/spi-to-axi-bridge | VHDLSystemVerilogProlog | 24 | 0 | 6 | 0 |
| bpadalino/vhdl-format | VHDLShell | 23 | 0 | 2 | 0 |
| ThalesGroup/udp-offload-engine | VHDL | 4 | 0 | 1 | 0 |
| VHDL-LS/rust_hdl | VHDLRust | 246 | 0 | 51 | 0 |
| jofrfu/tinyTPU | VHDLCPython | 305 | 0 | 58 | 0 |
| alialaei110/HDLab-FPGA-Development-Board | VHDL | 47 | 0 | 33 | 0 |
| seanpm2001/AI2001_Category-Source_Code-SC-VHDL | RRMarkdownVHDL | 2 | 0 | 1 | 0 |
| OSVVM/OSVVM | VHDLTcl | 195 | -1 | 52 | 0 |