bpadalino/vhdl-format

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VHDL String Formatting Package This is a VHDL string formatting package that is based on f-strings found in Python 3. Problem Working with strings in VHDL is somewhat difficult. They require known sizes, are concatenated with the & operator, and can be difficult to align concisely. A typical string building line might look like: report "int: " & integer'image(int) & " real: " & real'image(r); Solution VHDL has operator overloading which includes the return style, so we can emulate the...