| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| openhwgroup/cva6 | SystemVerilogCAssembly | 1.8k | +7 | 549 | +1 |
| WangXuan95/FPGA-SATA-HBA | SystemVerilogVerilogVHDL | 57 | +2 | 15 | 0 |
| WangXuan95/FPGA-MPEG2-encoder | VerilogBatchfile | 61 | +2 | 10 | 0 |
| openhwgroup/core-v-verif | AssemblySystemVerilogC | 328 | +1 | 183 | -1 |
| pulp-platform/axi | SystemVerilogStataShell | 791 | 0 | 222 | +3 |
| VUnit/vunit | VHDLPythonOther | 645 | 0 | 236 | 0 |
| pulp-platform/axi_mem_if | SystemVerilog | 27 | 0 | 21 | 0 |
| openhwgroup/core-v-mcu | SystemVerilogCC++ | 146 | 0 | 51 | 0 |
| WangXuan95/FPGA-SDcard-Reader | VerilogBatchfile | 153 | 0 | 42 | 0 |
| pulp-platform/axi_node | SystemVerilog | 17 | 0 | 35 | 0 |
| taichi-ishitani/tvip-axi | SystemVerilogOther | 248 | 0 | 83 | 0 |
| clash-lang/clash-compiler | HaskellCTcl | 1.3k | 0 | 143 | 0 |
| airhdl/spi-to-axi-bridge | VHDLSystemVerilogProlog | 24 | 0 | 6 | 0 |
| zachjs/sv2v | HaskellSystemVerilogVerilog | 404 | 0 | 46 | 0 |
| pulp-platform/pulp_soc | SystemVerilog | 62 | 0 | 74 | 0 |
| avashist003/SystemVerilog_Design_Verification | SystemVerilog | 19 | 0 | 3 | 0 |
| hdl-util/hdmi | SystemVerilogPythonStata | 911 | 0 | 98 | 0 |
| hanysalah/Design-Pattern-in-SV | SystemVerilog | 50 | 0 | 3 | 0 |
| WangXuan95/FpOC | VerilogBatchfile | 326 | 0 | 124 | 0 |
| WangXuan95/USTC-RVSoC | SystemVerilogAssemblyTcl | 267 | 0 | 65 | 0 |
| veripool/verilog-mode | SystemVerilogEmacs LispOther | 220 | 0 | 83 | 0 |
| chipsalliance/sv-tests | SystemVerilogPythonJavaScript | 237 | 0 | 64 | 0 |
| pezy-computing/pzbcm | SystemVerilogRuby | 22 | 0 | 1 | 0 |
| dshekhalev/FEC | SystemVerilogOther | 47 | 0 | 12 | 0 |
| sifferman/labs-with-cva6 | SystemVerilogAssemblyMakefile | 18 | 0 | 14 | 0 |