This is stars and forks stats for /avashist003/SystemVerilog_Design_Verification repository. As of 04 May, 2024 this repository has 19 stars and 3 forks.
| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| hdl-util/hdmi | SystemVerilogPythonStata | 911 | 0 | 98 | 0 |
| SeanOBoyle/DoxygenFilterSystemVerilog | PerlSystemVerilogHTML | 29 | 0 | 9 | 0 |
| Mazamars312/Analogue_Pocket_Neogeo | VerilogC++SystemVerilog | 235 | 0 | 10 | 0 |
| zephray/RISu64 | VerilogCPython | 50 | 0 | 8 | 0 |
| antmicro/yosys-uhdm-plugin-integration | VerilogC++Tcl | 80 | 0 | 12 | 0 |
| MiSTer-devel/NeoGeo_MiSTer | VerilogC++SystemVerilog | 123 | 0 | 75 | 0 |
| antmicro/yosys-systemverilog | VerilogC++Tcl | 80 | +2 | 12 | 0 |
| nandland/spi-master | VHDLVerilogSystemVerilog | 176 | 0 | 84 | 0 |
| firedancer-io/firedancer | CSystemVerilogPython | 472 | +2 | 73 | 0 |
| WangXuan95/FPGA-SATA-HBA | SystemVerilogVerilogVHDL | 57 | +2 | 15 | 0 |