chipsalliance/sv-tests

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SystemVerilog Tester The purpose of this project is to find all the supported and missing SystemVerilog features in various Verilog tools. The report generated from the last passing master build can be viewed on a dedicated dashboard: History of the builds is also tracked and can be seen on a separate page: Running Initialize the submodules: git submodule update --init --recursive Install all the python dependencies and make sure the installed binaries can be called. pip3 install --user -r conf/requirements.txt export...