| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| randyrossi/vicii-kawari | VerilogCAssembly | 142 | +1 | 18 | 0 |
| furrtek/VGChips | VerilogPython | 131 | +1 | 12 | 0 |
| chipsalliance/VeeRwolf | VerilogSystemVerilogTcl | 234 | +1 | 54 | +1 |
| risclite/R8051 | VerilogC | 125 | +1 | 39 | 0 |
| T-head-Semi/openc906 | VerilogAssemblyC | 244 | +1 | 76 | +1 |
| T-head-Semi/opene902 | VerilogCAssembly | 110 | +1 | 57 | +1 |
| sergeykhbr/riscv_vhdl | VerilogC++SystemVerilog | 537 | +1 | 96 | 0 |
| PKUanonym/REKCARC-TSC-UHT | HTMLCC++ | 29.7k | 0 | 7.3k | 0 |
| chipsalliance/chisel3 | ScalaC++Python | 3.2k | 0 | 541 | 0 |
| apache/tvm-vta | ScalaC++Tcl | 213 | 0 | 65 | 0 |
| pulp-platform/axi_riscv_atomics | SystemVerilogStataVerilog | 39 | 0 | 11 | 0 |
| efabless/caravel_user_project | VerilogOther | 130 | 0 | 294 | 0 |
| MiSTer-devel/PSX_MiSTer | VHDLVerilogSystemVerilog | 172 | 0 | 40 | 0 |
| aws/aws-fpga | VHDLSystemVerilogV | 1.4k | 0 | 516 | 0 |
| OSCPU/ysyx-workbench | ShellMakefileC++ | 63 | 0 | 72 | 0 |
| SpinalHDL/SpinalHDL | ScalaVerilogPython | 1.4k | 0 | 276 | 0 |
| chipsalliance/Cores-SweRV | SystemVerilogCPerl | 730 | 0 | 194 | 0 |
| riscv-mcu/e203_hbirdv2 | VerilogCAssembly | 923 | 0 | 287 | 0 |
| danfoisy/vdatp | VerilogHTMLC++ | 269 | 0 | 29 | 0 |
| pConst/basic_verilog | VerilogVHDLSystemVerilog | 1.3k | 0 | 303 | 0 |
| ucb-bar/nvdla-wrapper | VerilogOther | 15 | 0 | 7 | 0 |
| ucb-bar/sha3 | VerilogCScala | 72 | 0 | 19 | 0 |
| T-head-Semi/openc910 | VerilogAssemblyC | 906 | 0 | 248 | 0 |
| MoonbaseOtago/vroom | VerilogSystemVerilogHTML | 406 | 0 | 16 | 0 |
| ultraembedded/riscv | VerilogC++C | 933 | 0 | 192 | 0 |