chipsalliance/VeeRwolf

FuseSoC-based SoC for SweRV EH1 and EL2

VerilogSystemVerilogTclAssemblyCC++Othertoolsfusesocswerv
This is stars and forks stats for /chipsalliance/VeeRwolf repository. As of 27 Apr, 2024 this repository has 234 stars and 54 forks.

VeeRwolf VeeRwolf is a FuseSoC-based reference platform for the VeeR family of RISC-V cores. Currently, VeeR EH1 and VeeR EL2 are supported. See CPU configuration to learn how to switch between them. This can be used to run the RISC-V compliance tests, Zephyr OS, TockOS or other software in simulators or on FPGA boards. Focus is on portability, extendability and ease of use; to allow VeeR users to quickly get software running, modify the SoC to their needs or port it to new target devices. This project...
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