repo | techs | stars | weekly | forks | weekly |
---|---|---|---|---|---|
projf/projf-explore | SystemVerilogTclC++ | 455 | +1 | 47 | 0 |
ultraembedded/cores | VerilogCC++ | 575 | +1 | 185 | +2 |
openhwgroup/core-v-verif | AssemblySystemVerilogC | 328 | +1 | 183 | -1 |
syntacore/scr1 | SystemVerilogCMakefile | 689 | +1 | 240 | 0 |
bxinquan/zynq_cam_isp_demo | VHDLVerilogC | 115 | +1 | 51 | 0 |
randyrossi/vicii-kawari | VerilogCAssembly | 142 | +1 | 18 | 0 |
natelannan-osu/dldspring2023 | TeXSystemVerilogHTML | 2 | +1 | 19 | 0 |
pulp-platform/carfield | SystemVerilogPythonTcl | 25 | +1 | 3 | 0 |
chipsalliance/VeeRwolf | VerilogSystemVerilogTcl | 234 | +1 | 54 | +1 |
T-head-Semi/openc906 | VerilogAssemblyC | 244 | +1 | 76 | +1 |
sergeykhbr/riscv_vhdl | VerilogC++SystemVerilog | 537 | +1 | 96 | 0 |
muneeb-mbytes/pulpino__spi_master__ip_verification | SystemVerilogOther | 16 | 0 | 6 | 0 |
lowRISC/ibex | SystemVerilogPythonC++ | 1.1k | 0 | 447 | +2 |
pulp-platform/fpga-support | SystemVerilogMakefileTcl | 4 | 0 | 9 | 0 |
pulp-platform/axi_riscv_atomics | SystemVerilogStataVerilog | 39 | 0 | 11 | 0 |
pulp-platform/axi | SystemVerilogStataShell | 791 | 0 | 222 | +3 |
MiSTer-devel/PSX_MiSTer | VHDLVerilogSystemVerilog | 172 | 0 | 40 | 0 |
aws/aws-fpga | VHDLSystemVerilogV | 1.4k | 0 | 516 | 0 |
SpinalHDL/SpinalHDL | ScalaVerilogPython | 1.4k | 0 | 276 | 0 |
chipsalliance/Cores-SweRV | SystemVerilogCPerl | 730 | 0 | 194 | 0 |
pulp-platform/snitch | SystemVerilogCRust | 206 | 0 | 44 | 0 |
danfoisy/vdatp | VerilogHTMLC++ | 269 | 0 | 29 | 0 |
pConst/basic_verilog | VerilogVHDLSystemVerilog | 1.3k | 0 | 303 | 0 |
T-head-Semi/openc910 | VerilogAssemblyC | 906 | 0 | 248 | 0 |
pulp-platform/common_verification | SystemVerilogShell | 33 | 0 | 10 | 0 |