chipsalliance/synlig

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Synlig Synlig is a SystemVerilog and UHDM front end plugin for Yosys. It uses Surelog, a SystemVerilog 2017 preprocessor, parser and elaborator. Installation Before installing the plugin, check that Yosys is installed and correctly configured: yosys -version yosys-config --help The required Yosys version is 0.33 or later. If you don't have Yosys, skip to the Installation from source section to build Yosys from the source or follow the steps below for Debian-based Linux distributions: Debian...