aolofsson/oh

Verilog library for ASIC and FPGA designers

VerilogTclCShellPythonSystemVerilogOther
This is stars and forks stats for /aolofsson/oh repository. As of 25 Apr, 2024 this repository has 1001 stars and 268 forks.

======= OH! Open Hardware for Chip Designers Introduction !!! WARNING!!! Main branch is Work In Progress (ie broken) For a stable version, seee Tag V1.0 OH! is an open-source library of hardware building blocks based on silicon proven design practices at 0.35um to 28nm. The library is being used by Adapteva in designing its next generation ASIC. The library is written in standard Verilog (2005) and contains over 25,000 lines of Verilog code, over 150 separate modules. Examples of functionality include:...
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