| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| ghdl/ghdl | VHDLAdaC | 2k | +13 | 332 | +1 |
| universal-ctags/ctags | CC++M4 | 6k | +8 | 622 | 0 |
| RobertPeip/Mister64 | VHDLVerilogSystemVerilog | 112 | +8 | 10 | +1 |
| analogdevicesinc/hdl | VerilogTclMakefile | 1.2k | +5 | 1.4k | +3 |
| H4K3R13/The-Hello-World-Project | SchemeAssemblyWitcher Script | 24 | +5 | 51 | +9 |
| newaetech/chipwhisperer | VHDLCPython | 945 | +4 | 266 | +2 |
| stnolting/neorv32 | VHDLCMakefile | 1.2k | +4 | 172 | 0 |
| Digital-EDA/Digital-IDE | VerilogJavaScriptC++ | 72 | +4 | 4 | +1 |
| PacktPublishing/Learn-FPGA-Programming | VHDLVerilogV | 133 | +3 | 60 | +1 |
| MiSTer-devel/S32X_MiSTer | SystemVerilogVerilogVHDL | 46 | +2 | 15 | +1 |
| WangXuan95/FPGA-SATA-HBA | SystemVerilogVerilogVHDL | 57 | +2 | 15 | 0 |
| nickg/nvc | VHDLCM4 | 532 | +2 | 75 | 0 |
| EttusResearch/uhd | VerilogC++C | 844 | +1 | 620 | +1 |
| bxinquan/zynq_cam_isp_demo | VHDLVerilogC | 115 | +1 | 51 | 0 |
| jankae/LibreVNA | C++CVHDL | 683 | +1 | 138 | +1 |
| sergeykhbr/riscv_vhdl | VerilogC++SystemVerilog | 537 | +1 | 96 | 0 |
| MiSTer-devel/PSX_MiSTer | VHDLVerilogSystemVerilog | 172 | 0 | 40 | 0 |
| aws/aws-fpga | VHDLSystemVerilogV | 1.4k | 0 | 516 | 0 |
| SpinalHDL/SpinalHDL | ScalaVerilogPython | 1.4k | 0 | 276 | 0 |
| pConst/basic_verilog | VerilogVHDLSystemVerilog | 1.3k | 0 | 303 | 0 |
| greatscottgadgets/hackrf | CCMakePython | 5.6k | 0 | 1.4k | 0 |
| slaclab/surf | VHDLPythonSystemVerilog | 248 | 0 | 47 | 0 |
| tomas-fryza/digital-electronics-1 | VHDLTclOther | 55 | 0 | 229 | 0 |
| VUnit/vunit | VHDLPythonOther | 645 | 0 | 236 | 0 |
| opencomputeproject/Time-Appliance-Project | VHDLTclC | 1.3k | 0 | 89 | 0 |