| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| cxlisme/FPGA-proj | VHDLVerilogV | 145 | 0 | 38 | 0 |
| songshangru/BIT-CS-Learning | VHDLVerilogJava | 179 | 0 | 53 | 0 |
| KULeuven-COSIC/CryptoNightHaven-FPGA-miner | VHDLVerilogTcl | 6 | 0 | 2 | 0 |
| jhshi/openofdm | VerilogVHDLOther | 306 | 0 | 169 | 0 |
| pulp-platform/apb_uart | VHDLSystemVerilogTcl | 6 | 0 | 20 | 0 |
| MiSTer-devel/Arcade-Cave_MiSTer | ScalaVerilogSystemVerilog | 73 | 0 | 17 | 0 |
| yunwei37/ZJU-CS-GIS-ClassNotes | Jupyter NotebookVerilogC | 783 | 0 | 160 | 0 |
| MiSTer-devel/ao486_MiSTer | VerilogCC++ | 220 | 0 | 59 | 0 |
| mjbrown/umn_simaudio | VHDLVerilogTcl | 7 | 0 | 4 | 0 |
| firesim/aws-fpga-firesim | VHDLVerilogV | 10 | 0 | 8 | 0 |
| slaclab/amc-carrier-core | VHDLTclPython | 2 | 0 | 3 | 0 |
| ZipCPU/wb2axip | VerilogMakefileC++ | 384 | 0 | 90 | 0 |
| slaclab/lcls-timing-core | VHDLPythonVerilog | 2 | 0 | 3 | 0 |
| robmdunn/yams | VHDL | 0 | 0 | 0 | 0 |
| MiSTer-devel/SNES_MiSTer | VHDLVerilogSystemVerilog | 167 | 0 | 69 | 0 |
| ViacheslavL/vhdl_examples | VHDL | 0 | 0 | 0 | 0 |
| srg320/Saturn_MiSTer | SystemVerilogVerilogVHDL | 138 | 0 | 19 | 0 |
| Ryzee119/OpenXenium | VHDL | 211 | 0 | 42 | 0 |
| spark2k06/PCXT_MiSTer | SystemVerilogVerilogAssembly | 46 | 0 | 15 | 0 |
| MiSTer-devel/GnW_MiSTer | VerilogSystemVerilogVHDL | 12 | 0 | 9 | 0 |
| antonblanchard/microwatt | VerilogVHDLC | 569 | 0 | 96 | 0 |
| jgrahsl/stereovision | VHDLPythonShell | 2 | 0 | 4 | 0 |
| slaclab/epix-hr-core | VHDLPythonTcl | 1 | 0 | 0 | 0 |
| slaclab/axi-pcie-core | VHDLTclSystemVerilog | 14 | 0 | 9 | 0 |
| airhdl/spi-to-axi-bridge | VHDLSystemVerilogProlog | 24 | 0 | 6 | 0 |