alexforencich/verilog-axi

Verilog AXI components for FPGA implementation

VerilogPythonMakefileTcl
This is stars and forks stats for /alexforencich/verilog-axi repository. As of 25 Apr, 2024 this repository has 1058 stars and 361 forks.

Verilog AXI Components Readme For more information and updates: http://alexforencich.com/wiki/en/verilog/axi/start GitHub repository: https://github.com/alexforencich/verilog-axi Introduction Collection of AXI4 and AXI4 lite bus components. Most components are fully parametrizable in interface widths. Includes full cocotb testbenches that utilize cocotbext-axi. Documentation axi_adapter module AXI width adapter module with parametrizable data and address interface widths. Supports INCR burst types...
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