OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

VerilogC++TclCCMakeYaccparallel-computingedacircuit-simulatorcadverilogcpp17circuit-simulationvlsicircuit-analysiscomputer-aided-designvlsi-physical-designstaelectronic-design-automationvlsi-circuitsstatic-timing-analysis
This is stars and forks stats for /OpenTimer/OpenTimer repository. As of 02 May, 2024 this repository has 472 stars and 139 forks.

OpenTimer A High-Performance Timing Analysis Tool for VLSI Systems Why OpenTimer? OpenTimer is a new static timing analysis (STA) tool to help IC designers quickly verify the circuit timing. It is developed completely from the ground up using C++17 to efficiently support parallel and incremental timing. Key features are: Industry standard format (.lib, .v, .spef, .sdc) support Graph- and path-based timing analysis Parallel incremental timing for fast timing closure Award-winning tools and golden...
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