This is stars and forks stats for /alexforencich/verilog-uart repository. As of 29 Apr, 2024 this repository has 313 stars and 110 forks.
Verilog UART Readme For more information and updates: http://alexforencich.com/wiki/en/verilog/uart/start GitHub repository: https://github.com/alexforencich/verilog-uart Introduction This is a basic UART to AXI Stream IP core, written in Verilog with cocotb testbenches. Documentation The main code for the core exists in the rtl subdirectory. The uart_rx.v and uart_tx.v files are the actual implementation, uart.v simply instantiates both modules and makes a couple of internal connections. The UART...
Verilog UART Readme For more information and updates: http://alexforencich.com/wiki/en/verilog/uart/start GitHub repository: https://github.com/alexforencich/verilog-uart Introduction This is a basic UART to AXI Stream IP core, written in Verilog with cocotb testbenches. Documentation The main code for the core exists in the rtl subdirectory. The uart_rx.v and uart_tx.v files are the actual implementation, uart.v simply instantiates both modules and makes a couple of internal connections. The UART...
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