zephray/RISu64

Dual-issue RV64IM processor for fun & learning

VerilogCPythonC++SystemVerilogMakefileOtherrisc-v
This is stars and forks stats for /zephray/RISu64 repository. As of 27 Apr, 2024 this repository has 50 stars and 8 forks.

RISu064 RISu64 (Reduced Instruction Set μProcessor 64 / Squirrel 64) is a series of my toy 64-bit RISC-V compatible processors. RISu064 (this repo) is the first in the series. Illustration by Andy Lithia. Features RV64IMZicsr_Zifencei instruction set 7-stage pipeline: PCGen(F1), IMem(F2), Decode(ID), Issue(IX), Execute(EX), DMem(MEM), Writeback(WB). In-order issue and out-of-order writeback Dual-issue BTB + Bimodal/Gselect/Gshare/Tournament + RAS branch predictors 2x Integer (arithmetic, barrel shifter,...
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