This is stars and forks stats for /b224hisl/rioschip repository. As of 30 Apr, 2024 this repository has 29 stars and 3 forks.
HEHECORE Overview This is a small out-of-order RISC-V core written in synthesizable Verilog that supports the RV64IC unprivileged ISA and parts of the privileged ISA, namely M-mode. Feature List It currently supports RISC-V I extension It currently supports M mode It's a double issue architecture It supports scalar register renaming It currently supports only in-order issue from the issue queue It has a ROB to do in-order committment When an exception or an interrupt happens, the ROB will be responsible...
HEHECORE Overview This is a small out-of-order RISC-V core written in synthesizable Verilog that supports the RV64IC unprivileged ISA and parts of the privileged ISA, namely M-mode. Feature List It currently supports RISC-V I extension It currently supports M mode It's a double issue architecture It supports scalar register renaming It currently supports only in-order issue from the issue queue It has a ROB to do in-order committment When an exception or an interrupt happens, the ROB will be responsible...
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