| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| ucb-bar/chipyard | CScalaMakefile | 1.2k | 0 | 532 | 0 |
| chipsalliance/sv-tests | SystemVerilogPythonJavaScript | 237 | 0 | 64 | 0 |
| verilator/verilator | C++SystemVerilogPerl | 1.8k | 0 | 462 | 0 |
| layoutBox/PinLayout | SwiftObjective-COther | 2.2k | 0 | 135 | 0 |
| pezy-computing/pzbcm | SystemVerilogRuby | 22 | 0 | 1 | 0 |
| epsilon537/boxlambda | VerilogCTcl | 26 | 0 | 0 | 0 |
| chipsalliance/Cores-VeeR-EH1 | SystemVerilogCPerl | 730 | 0 | 194 | 0 |
| joecupano/SIGpi | Shell | 128 | 0 | 12 | 0 |
| wiedehopf/tar1090 | JavaScriptHTMLShell | 1000 | 0 | 195 | 0 |
| shajen/rtl-sdr-scanner-cpp | C++CMakeDockerfile | 472 | 0 | 47 | 0 |
| pulp-platform/cheshire | SystemVerilogCTcl | 56 | 0 | 12 | +1 |
| efabless/openlane2 | PythonTclNix | 70 | 0 | 6 | 0 |
| chipsalliance/Cores-VeeR-EL2 | SystemVerilogPythonPerl | 194 | 0 | 55 | 0 |
| 4xmen/Web-Package-RTL | HTMLSCSSJavaScript | 313 | 0 | 88 | 0 |
| KASIRGA-KIZIL/tekno-kizil | VerilogAssemblyC | 130 | 0 | 9 | 0 |
| WangXuan95/FPGA-JPEG-LS-encoder | VerilogBatchfile | 134 | 0 | 26 | 0 |
| openasic-org/xkISP | VerilogC++Tcl | 159 | -1 | 81 | 0 |