bsg-external/ee477-hammer-cad

TclPythonMakefileVerilog
This is stars and forks stats for /bsg-external/ee477-hammer-cad repository. As of 29 Apr, 2024 this repository has 0 stars and 0 forks.

Complex Digital VLSI System Design Labs AKA: "VLSI II", EE 477, EE 525, CSE 567 Winter Quarter 2023 The labs for this course use the newly created Phoenix VLSI Flow. This CAD flow is based on UCB-BAR's Hammer VLSI flow. The labs are divided into 4 modules (0-3) followed by a final project. Getting Started Links Course Home Page Linux Tutorial Git Tutorial Summary of Make Targets Many of these targets also have a “redo” variant. By prepending “redo-” to the target, The same target will be run, but...
Read on GithubGithub Stats Page
repotechsstarsweeklyforksweekly
MiSTer-devel/Arcade-MrJong_MiSTerVerilogVHDLSystemVerilog0030
chrisbra/DistractFreeVim ScriptMakefilePerl17030
kkos/onigurumaCShellPython2.1k03040
cuifengcn/wechat-video-generateCSSPythonHTML3080920
mjbommar/gpt-takes-the-bar-examHTMLJupyter NotebookPython1390170
QuiteAFancyEmerald/Holy-UnblockerHTMLJavaScriptCSS36802.2k0
stevearc/oil.nvimLuaPythonOther1.3k0270
remerge/ansible-role-grafana-agentMakefileJinja0010
andresantoro/RHOSTSPLSQLJupyter NotebookPython31070
helblazer811/ManimMLPythonMakefile1.5k0850