UBC-CPEN311-Classrooms/2022w1-lab4-update1

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Deep Neural Networks on FPGA Contents Background Deep neural networks Q16.16 fixed point Design Task 1: Tutorials Task 2: PLL and SDRAM controller Task 3: Simulation Task 4: Wrapping the VGA core Task 5: A memory copy accelerator Task 6: A dot product accelerator Task 7: A faster dot product accelerator Optional Task 8: A complete neural network accelerator Additional specifications Avalon protocol variant Memory map Test inputs Common problems Deliverables and Evaluation Marks Breakdown Autograder...