This is stars and forks stats for /scalable-arch/100kSV repository. As of 30 Apr, 2024 this repository has 1 stars and 9 forks.
100kSV 100k lines of SystemVerilog to be a Computer Architect or VLSI front-end expert. Resources: Synopsys DesignWare Building Blocks https://www.synopsys.com/dw/buildingblock.php HDLBits https://hdlbits.01xz.net/wiki/Main_Page Module 1: Structural SystemVerilog (Transistor-level) Inverter NAND2 NOR2 AND2 OR2 XOR2 XNOR2 AND-OR-Inverter 21 OR-AND-Inverter 2:1 Mux 1:2 demux RS latch D flip flop JK flip flop Module 2: Structural SystemVerilog (Gate-level) XOR2 XNOR2 2:1 Mux 1:2 demux Half-adder Full-adder RS...
100kSV 100k lines of SystemVerilog to be a Computer Architect or VLSI front-end expert. Resources: Synopsys DesignWare Building Blocks https://www.synopsys.com/dw/buildingblock.php HDLBits https://hdlbits.01xz.net/wiki/Main_Page Module 1: Structural SystemVerilog (Transistor-level) Inverter NAND2 NOR2 AND2 OR2 XOR2 XNOR2 AND-OR-Inverter 21 OR-AND-Inverter 2:1 Mux 1:2 demux RS latch D flip flop JK flip flop Module 2: Structural SystemVerilog (Gate-level) XOR2 XNOR2 2:1 Mux 1:2 demux Half-adder Full-adder RS...
| repo | techs | stars | weekly | forks | weekly |
|---|---|---|---|---|---|
| phoeniX-Digital-Design/phoeniX | VerilogShellAssembly | 22 | 0 | 1 | 0 |
| sipeed/TangMega-138KPro-example | GLSLVerilogHTML | 10 | 0 | 1 | 0 |
| yuri-panchul/systemverilog-homework | SystemVerilogShellBatchfile | 1 | 0 | 4 | +1 |
| LELEC210X/LELEC210X | VHDLCVerilog | 1 | 0 | 14 | 0 |
| PixelExperience-Devices/device_qcom_common | MakefileShellForth | 12 | 0 | 10 | 0 |