openhwgroup/cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P

SystemVerilogM4VerilogOther
This is stars and forks stats for /openhwgroup/cv32e40s repository. As of 03 May, 2024 this repository has 112 stars and 18 forks.

OpenHW Group CORE-V CV32E40S RISC-V IP CV32E40S is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements the following instruction set architecture: RV32[I|E] [M|Zmmul] Zca_Zcb_Zcmp_Zcmt Xsecure [Zba_Zbb_Zbs|Zba_Zbb_Zbc_Zbs] Zicsr Zifencei The CV32E40S core is aimed at security applications and offers both Machine mode and User mode, an enhanced PMP, as well as various anti-tampering features. It started its life as a fork of the OpenHW CV32E40P core that in...
Read on GithubGithub Stats Page
repotechsstarsweeklyforksweekly
TdP-esami/2020-06-10-simulazioneTSQLOther202710
yessGlory17/programmer-browserTypeScriptJavaScriptCSS5810130
EsperoTech/yaadeTypeScriptKotlinCSS1.2k0490
monkeytypegame/monkeytypeTypeScriptHTMLSCSS11.8k01.8k0
BYVoid/OpenCCC++PythonCMake7.6k09490
ErLinErYi/PlantsVsZombiesC++Objective-CC1.5k02390
k9mail/k-9KotlinJavaOther8.4k02.4k0
beefproject/beefJavaScriptRubyCSS8.8k02k0
hasinhayder/hydraPHPBladeOther89001350
shlinkio/shlinkPHPOther2.3k02010