BrunoLevy/learn-fpga

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learn-fpga Learning FPGA, yosys, nextpnr, and RISC-V Mission statement: create teaching material for FPGAs, processor design and RISC-V, using around $40 per students. FemtoRV: a minimalistic RISC-V CPU FemtoRV is a minimalistic RISC-V design, with easy-to-read Verilog sources directly written from the RISC-V specification. The most elementary version (quark), an RV32I core, weights 400 lines of VERILOG (documented version), and 100 lines if you remove the comments. There are also more elaborate...