bol-edu/caravel-soc

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全端IC設計工程師養成計劃 (FullStack IC Designer Development) The FullStack IC Designer Development will base on the Caravel SoC backbone. We target two ASIC tapeouts: Google Efabless SKY130 with open source EDA flow (Openlane & Efabless Caravel) and TSMC 0.18um with commercial EDA flow. We also plan to develop a validation system for the chips that come back as verification. FullStack IC Designer Development Caravel SoC Caravel SoC is a platform for developing RISC-V CPU based hardware and software referred...